(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating an improved buried strap in deep trench DRAM devices in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, a buried strap has been used in fabricating deep trench (DT)-based dynamic random access memory (DRAM) devices. The buried strap is a crucial part of the integration step connecting a storage node capacitor to an array switching transistor by forming a diffusion junction. Therefore, control of diffusion length and resistivity of the buried strap are key issues for a healthy interconnect between array devices and capacitors. The diffusion length and resistivity primarily depend upon buried strap width and thickness and thermal budget during post processes.
In a conventional deep trench process, a deep trench is etched. A sacrificial layer fills the trench. A first recess, recess 1, is formed by removing the sacrificial layer from an upper portion of the trench. A dielectric collar is formed conformally in the upper portion of the deep trench. The sacrificial layer is removed, buried plate doping and node dielectric are formed, and a polysilicon layer fills the trench. A second recess, recess 2, is formed to lower the top surface of the polysilicon layer below the substrate surface. A portion of the collar is removed and a second doped polysilicon layer is deposited and planarized by CMP. Now, a third recess, recess 3, is formed to lower the second polysilicon layer below the substrate surface. The buried strap is formed by dopant out-diffusion from the recessed second polysilicon layer during post recess 3 thermal processes.
However, this conventional scheme cannot accurately control the buried strap depth, thickness, and doping level because of the complex interactions of the recess 2, collar removal, and recess 3 steps. Thus, the buried strap junction diffusion is poorly controlled. The recess 3 depth is especially hard to control inasmuch as it is sensitive to both remaining silicon nitride thickness and critical dimension which are varying. A shallow etch results in over diffusion causing short channel effects while a deep etch results in an open circuit, cutting off the current path. This limited controllability makes the BuriEd STrap (BEST) DRAM cell extendibility limited to a shorter generation.
A number of patents have addressed aspects of DRAM fabrication. U.S. Pat. No. 6,211,006 to Tsai et al shows a trench-type capacitor. U.S. Pat. No. 6,124,206 to Flietner et al teaches forming deep trench capacitors. U.S. Pat. No. 6,080,618 to Bergner et al discloses formation of a buried strap with little thickness variation. The buried strap is formed where the collar is partially removed. U.S. Pat. No. 6,008,104 to Schrems shows a BEST DRAM process. U.S. Pat. No. 5,981,332 to Mandelman et al shows a BEST DRAM process.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of BEST DRAM formation in the fabrication of integrated circuits.
It is a further object of the invention to provide a method of forming an improved buried strap in DRAM device fabrication.
Another object of the invention is to provide an improved buried strap formation method using a selective hemispherical grain (HSG) method in the fabrication of a DRAM integrated circuit device.
Yet another object of the invention is to provide an improved buried strap formation method using plasma doping in the fabrication of a DRAM integrated circuit device.
A further object of the invention is to provide an improved buried strap formation method having a ground rule of less than or equal to 0.25 xcexcm in the fabrication of a DRAM integrated circuit device.
A still further object of the invention is to provide an improved buried strap formation method using a selective HSG method along with plasma doping in the fabrication of a DRAM integrated circuit device.
In accordance with the objects of the invention, an improved buried strap method in the fabrication of a DRAM integrated circuit device is achieved. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.